This invention relates to a high-speed serial interface, especially in a programmable logic device (PLD), which may operate at different data rates.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (Extended Attachment Unit Interface) standard. In accordance with the XAUI standard for example, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
In one implementation, each transceiver is divided into a physical medium attachment (PMA) portion or module which communicates with outside devices, and a physical coding sublayer (PCS) portion or module which performs serial processing of data, for transmission to, or that is received from, those outside devices.
Even when operating under identical standards, a particular serial interface may operate at different speeds, depending, for example, on line conditions. Thus, it is known for the PCS of a serial interface to negotiate with its counterpart for the highest speed that will support reliable transmission and reception at both ends. Heretofore, however, such negotiation has been carried out in software or in the programmable logic core of the programmable logic device, outside of the serial interface itself.
Newer emerging serial protocols, such as PCI Express Generation 2 (“PCIe2”), 4 Gbps Fibre Channel (“4GFC”) and 8 Gbps Fibre Channel (“8GFC”), have short speed negotiation windows. These windows generally are too short for the relatively slow software or programmable logic.
It would be desirable to be able to provide faster (i.e., lower latency) speed negotiation in the PCS of a serial interface in a programmable logic device.